I've seen a Xilinx FPGA, programmed to drive a CMOS analog row/column multiplexor on an imager, trash the multiplexor because the sub-nanosecond Xilinx digital edges went FAR BELOW ground, and FAR ABOVE the VDD. This was observable with a 1pF probe of 900MHz speed (the TEK active fet probe P6201, long obsolete). Your normal 13pF slow probe showed no overshoot.
I was directed, by people with years of experience in these areas, to place a 1Kohm resistor in each of the 6" wires (about 15 of these wires) from Xilinx to the multiplexor. Result? A fine image, with lots of offset/gain error, appeared.
Some hot-cold plate correction was added, and you could see the heat of your finger soaking thru a sheet of paper.
What was going on? The protection diodes, expected to absorb ESD hits of either polarity, were turning on during those sub-nanosecond under/overshoots. Thus millions of times a second, charge was injected into the CMOS substrate and wells, upsetting the digital behavior and perhaps the analog signals if those were driven to grd/rail by unexpected flow of charges needing a path back home.
I've assisted in debugging other CMOS circuits, where just one logic gate was upset during an ESD test, because there was no local charge-gathering contact into well/substrate.